This application is a division of application Ser. No. 11/181,724, filed Jul. 15, 2005, now U.S. Pat. No. 7,256,447, which claims the benefit of Korean Patent Application No. 10-2004-0091491, filed on Nov. 10, 2004, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
1. Field of the Disclosure
Embodiments of the present disclosure include a semiconductor memory device, and more particularly, to a multi-bit non-volatile memory (NVM) device, a method of operating the same, and a method of manufacturing the multi-bit NVM device.
2. Description of the Related Art
Semiconductor memory devices are categorized into volatile memory devices and non-volatile memory (NVM) devices. Volatile memory devices, such as DRAMs, have been used in, for example, computers in order to store data in a hard disk and to process data in a short time when power is supplied.
However, as demand for mobile phones and digital cameras increases, demand for NVM devices also increases due to their advantages over DRAMs, which are used in computers. For example, NVM devices can process data in a short time, and store data even when power is no longer supplied.
An example of NVM devices is a flash memory device with a storage node. Depending on the type of the storage node, flash memory devices are classified into floating gate devices, and SONOS devices with oxide/nitride/oxide (ONO) structures. A conventional flash memory device will now be described.
FIG. 1 is a sectional view of a conventional floating gate flash memory device 100.
Referring to FIG. 1, the conventional flash memory device 100 includes a floating gate 120 which is used as a storage node, and is insulated from a control gate 130 by an inter-gate insulating film 125. In addition, the floating gate 120 is insulated from a semiconductor substrate 105 by a gate insulating film 115.
In the conventional flash memory device 100 shown in FIG. 1, when a voltage is applied to the control gate 130, charge tunneling occurs through the gate insulating film 115 and charges are stored in the floating gate 120. Alternatively, a voltage can be applied to a source/drain region 110 of the semiconductor substrate 105 to generate hot carriers that are injected into the floating gate 120.
In this case, cells are arranged in an array on the entire surface of the semiconductor substrate 105, thus increasing the integrity of the flash memory device. Recently, NAND array flash memory devices have been used in high-capacity devices due to their high integrity.
FIG. 2 is a sectional view of a conventional SONOS flash memory device 150.
Referring to FIG. 2, the conventional SONOS-type flash memory device 150 includes a nitride layer 170 that is used as a storage node. The nitride layer 170 is insulated from a semiconductor substrate 155 and a control gate 180 by oxide layers 165 and 175, respectively.
In this structure, when a voltage is applied to the control gate 180 and a source/drain region 160 of the semiconductor substrate 155, hot carriers are injected into the nitride layer 170. On the other hand, when a high-voltage is applied to the semiconductor substrate 155, charges existing in the nitride layer 170 are removed.
The conventional memory devices 100 and 150 shown in FIGS. 1 and 2 have a planar array structure. However, to increase integrity and capacity, many efforts have been made to develop a memory device with a three-dimensional array structure. In addition, methods of operating a unit cell in multi bits in order to increase a memory capacity have been developed.